1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly to a semiconductor memory which is preferably applied to a full CMOS static RAM.
2. Description of the Prior Art
In a stacked full CMOS static RAM obtained by stacking a load transistor consisting of a thin film transistor (TFT) on a driver transistor, low power consumption and good data retention characteristics can he obtained, and an integration density can he increased by stacking transistors. Therefore, the static RAM has received a great deal of attention in recent years.
A stacked full CMOS static RAM having a structure obtained by stacking load transistors consisting of TFTs on the gate electrode of a driver transistor using the gate electrode in common is proposed (Nikkei Micro Device, September issuer 1988, pp. 123-1130).
A stacked full CMOS static RAM in which the gate electrode of a driver transistor and the gate electrode of a load transistor consisting of a TFT are independently formed to make the channel length of the load transistor to he longer than the channel length of the driver transistor is proposed (IEDM, 1988, pp. 48-59).
In the conventional stacked full CMOS static RAM including a structure obtained by stacking a load transistor consisting of a TFT on a driver transistor so as to use a gate electrode in common, since the load transistor has an offset gate structure, a leakage current of the load transistor can be suppressed. However, the leakage current can not be satisfactorily reduced.
In the conventional stacked full CMOS static RAM in which the gate electrode of the driver transistor and the gate electrode of the load transistor are independently formed so as to increase the channel length of the load transistor, a channel length of 1.5 .mu.m or more required for reducing a leakage current is difficult to assure.